Models & Labs
Llama.cpp b10985 Release Enhances Hash-Cache Efficiency
llama.cpp Releaseshigh confidence
Why it matters
- →Optimizes server-side storage by reducing unnecessary cache entries.
- →Enhances performance in multi-node setups with large data transfers.
- →Updates RPC protocol for more efficient cache management.
Llama.cpp's b10985 release focuses on enhancing the efficiency of hash-cache management for tensor weights. The update introduces a refined process where only weights above a specific threshold are hashed and stored, reducing unnecessary disk usage. This is particularly beneficial in setups like Qwen3.8-Flash-Next, where large data transfers occur. Additionally, the RPC protocol has been updated to better signal cache decisions, ensuring only necessary data is cached. These improvements aim to optimize server performance and resource management for developers.
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llama.cpp b10993 adds ROCm 10 and CUDA 13 builds
This release quietly extends llama.cpp's hardware support to the latest driver stacks, adding official binaries for ROCm 10.0 and CUDA 13 across Linux and Windows. For AMD users, this means native compatibility with newer GPU architectures without manual compilation tweaks, while NVIDIA users gain access to the latest CUDA runtime optimizations. The inclusion of WebGPU in CI signals ongoing work toward browser-based inference, though it remains a background effort for now. There are no new model formats or quantization methods here, just broader infrastructure coverage that keeps llama.cpp relevant as hardware evolves.
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llama.cpp fixes Metal NaN bug for large activations
A critical precision bug in llama.cpp’s Apple Silicon backend has been patched, resolving total inference failures on models with high-activation ranges like Mistral Small 4. The issue stemmed from f16 saturation during matrix multiplication, which turned entire output tensors into NaN values for inputs exceeding ~32 tokens. By implementing an exact, power-of-two rescaling mechanism in the Metal kernel, the fix restores correctness without significant performance penalties. This ensures local inference on M-series chips remains viable for complex MoE architectures that previously crashed.
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